Smart driver for flyback converters

ABSTRACT

The present invention discloses a smart driver used in flyback converters adopting a transconductance amplifier to turn on a synchronous rectifier FET, and a comparator to quickly turn off the synchronous rectifier FET.

FIELD OF THE INVENTION

The present invention relates to flyback converters, and more particularly to flyback converters using synchronous rectification.

BACKGROUND ART

The majority of notebook power adapters use a flyback converter as shown in FIG. 1. To improve efficiency over diode rectification, most notebook power adapter manufacturers use synchronous rectification (SR). In other words, a synchronous rectifier FET is used to replace diode D on the secondary winding T₁ of the transformer T in the flyback converter shown in FIG. 1. A major disadvantage of SR over diode rectification is the higher cost, which is associated with the control signal that needs to be sent across the isolation barrier (the transformer).

Instead of sending the control signal across the isolation barrier, in certain prior art systems, the signal can also be derived from the voltage across the synchronous rectifier FET. One of the issues in doing this is that the voltage signal across the FET is very small compared to the dynamic range (millivolts versus tens of volts). To avoid false triggering, bandwidth is sacrificed. This leads to increased turn-off times, leading to efficiency losses.

Some prior art systems use a transconductance amplifier to slow the turn on of the synchronous rectifier FET, which solves the false triggering problem. However, slow turn-on makes it not useful in continuous conduction mode (CCM) applications. Furthermore, the transconductance amplifier brings a slow turn-off, which causes even more switching losses.

Therefore, there is an unmet need to provide a solution having a much faster turn-off and hence reduced switching losses. Moreover, the solution should be used in any type of flyback converter (CCM, discontinuous conductance mode (DCM), and quasi-resonant).

BRIEF DESCRIPTION OF THE DRAWINGS

The accompanying drawings, which are incorporated in and form a part of this specification, illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention.

FIG. 1 illustrates a prior art flyback converter.

FIG. 2 illustrates a circuit 100 using a transconductance amplifier to turn on a synchronous rectifier FET and uses a comparator to turn off the synchronous rectifier FET in accordance with an embodiment of the present invention.

DETAILED DESCRIPTION OF THE INVENTION

Reference will now be made in detail to the preferred embodiments of the invention, examples of which are illustrated in the accompanying drawings. While the invention will be described in conjunction with the preferred embodiments, it will be understood that they are not intended to limit the invention to these embodiments. On the contrary, the invention is intended to cover alternatives, modifications and equivalents, which may be included within the spirit and scope of the invention as defined by the appended claims. Furthermore, in the following detailed description of the present invention, numerous specific details are set forth in order to provide a thorough understanding of the present invention. However, the present invention may be practiced without these specific details. In other instances, well-known methods, procedures, components, and circuits have not been described in detail so as not to unnecessarily obscure aspects of the present invention.

Now referring to FIG. 2, a circuit 100 using a transconductance amplifier U₀ to turn on a synchronous rectifier FET M₁, and using a comparator U₁ to turn off the synchronous rectifier FET M₁ is illustrated. As shown in FIG. 2, circuit 100 comprises the transconductance amplifier U₀ receiving a first DC offset V₁ at its non-inverting input terminal and receiving a “V_(D)” signal at its inverting input terminal, wherein the V_(D) signal is the drain signal of the synchronous rectifier FET M₁. The drain signal V_(D) is also sent to the non-inverting input terminal of the comparator U₁, while the comparator U₁ receives a second DC offset V₂ at its inverting input terminal.

The output of the transconductance amplifier U₀ is sent to the gate of M₁ directly, and the output of the comparator U₁ is sent to the gate of M₁ via an internal switch S₁. When the output of the comparator U₁ is high, the internal switch S₁ is turned on, pulling the gate of M₁ to be low. When the output of the comparator U₁ is low, the internal switch S₁ is turned off, releasing the gate of M₁ to be controlled by the output of the transconductance amplifier U₀. A diode D₁ is a parasitic diode that comes with M₁ and is used to clamp V_(D) to a certain negative voltage such as −0.7V during D₁'s turn-on.

In operation, if the flyback converter is in continuous current mode, when a main switch on the primary winding T₀ in the flyback converter is turned off, the diode D₁ is on immediately, which causes V_(D) to be negative, such as −0.7V. As a result, the output of the transconductance amplifier U₀, i.e. V_(G) signal goes high gradually. When V_(G) increases to the on-threshold of M₁, M₁ is turned on accordingly. With the turn-on of M₁, the diode D₁ is off.

When the main switch on the primary winding T₀ in the flyback converter is turned on, V₀ goes high due to the induced voltage across the secondary winding T₁, which causes the output of the transconductance amplifier U₀ to be low, i.e., V_(G) is low. In the meantime, V_(D) goes higher than the second DC offset V₂, and the comparator U₁ outputs a high level signal, which turns on the internal switch S₁, and pulls low V_(G). As a result, the synchronous rectifier FET M₁ is quickly turned off.

If the flyback converter is in DCM or quasi resonant mode, when the main switch on the primary winding T₀ in the flyback converter is turned off, circuit 100′s operation is same to that in CCM. However, when the main switch on the primary winding T₀ in the flyback converter is turned on, the voltage on V_(D) goes up slowly. Then the transconductance amplifier U₀ will cause V_(G) to go low and the comparator is not used. Such operation also turns off the synchronous rectifier FET M₁.

To avoid the transconductance amplifier U₀ and the comparator U₁ “fighting” each other, a dead band is introduced, which is the voltage difference between V₁ and V₂. When V_(D) drops below V₁, the transconductance amplifier U₀ tries to keep V_(D) at the V₁ level by regulating V_(G). When V_(D) is moving so fast that the transconductance U₀ can't hold V_(D) to V₁, V_(D) will go up and at a certain instant will hit V₂. If that happens, the comparator U, turns on an internal switch S₁, which swiftly pulls low V_(G). This will turn off M₁ and no current will flow anymore, preventing shoot through.

Many modifications and variations of the present invention are possible in light of the above teachings. It is therefore to be understood that within the scope of the appended claims the invention may be practiced otherwise than as specifically described. It should be understood, of course, the foregoing disclosure relates only to a preferred embodiment (or embodiments) of the invention and that numerous modifications may be made therein without departing from the spirit and the scope of the invention as set forth in the appended claims. Various modifications are contemplated and they obviously will be resorted to by those skilled in the art without departing from the spirit and the scope of the invention as hereinafter defined by the appended claims as only a preferred embodiment(s) thereof has been disclosed. 

1. A driver circuit for driving a synchronous rectifier FET, comprising: a transconductance amplifier having a first input coupled to a first DC offset, a second input coupled to the drain of the synchronous rectifier FET, and an output coupled to the gate of the synchronous rectifier FET; and a comparator having a first input coupled to a second DC offset, a second input coupled to the drain of said synchronous rectifier FET, and an output coupled to the gate of the synchronous rectifier FET via a switch.
 2. The driver circuit of claim 1, wherein the synchronous rectifier FET is turned on according to an “on” state of a parasitic diode of the synchronous rectifier FET, and when the synchronous rectifier FET is turned on, the parasitic diode is off.
 3. The driver circuit of claim 1, wherein If a drain signal of the synchronous rectifier FET increases slowly, the output of the transconductance amplifier turns low to turn off the synchronous rectifier FET; and if the drain signal of the synchronous rectifier FET increases fast, the output of the comparator turns high to turn off the synchronous rectifier FET via the switch.
 4. The driver circuit of claim 1, wherein there is a voltage difference between the first DC offset and the second DC offset.
 5. The driver circuit of claim 1, wherein if the output of the comparator is high, the switch is turned on; if the output of the comparator is low, the switch is turned off.
 6. A smart driver comprising: a transconductance amplifier, operable to amplify the difference between a drain signal of a synchronous rectifier FET and a first DC offset to provide an amplified signal, and to control the synchronous rectifier FET using the amplified signal; and a comparator operable to compare the drain signal of the synchronous rectifier FET and a second DC offset to provide a comparison signal, and to control the synchronous rectifier FET by the comparison signal.
 7. The smart driver of claim 6, wherein the comparator controls the synchronous rectifier FET via a switch.
 8. The smart driver of claim 6, wherein there is a parasitic diode coming with the synchronous rectifier FET, when the parasitic diode is on, the drain signal of said synchronous rectifier FET is negative.
 9. The smart driver of claim 8, wherein the synchronous rectifier FET is turned on according to the “on” state of the parasitic diode; and when the synchronous rectifier FET is turned on, the parasitic diode is off.
 10. The smart driver of claim 7, wherein if the drain signal of said synchronous rectifier FET increases slowly, the amplified signal turns off the synchronous rectifier FET; and if the drain signal of the synchronous rectifier FET increases fast, the comparison signal turns off the synchronous rectifier FET via the switch.
 11. The smart driver of claim 6, wherein there is a voltage difference between the first DC offset and the second DC offset.
 12. The smart driver of claim 7, wherein if the comparison signal is high, the switch is turned on; and if the comparison signal is low, the switch is turned off.
 13. A method comprising: providing a drain signal of a synchronous rectifier FET to a first input of a transconductance amplifier and to a first input of a comparator; providing a first DC offset to a second input of the transconductance amplifier; providing a second DC offset to a second input of the comparator; delivering the output of the transconductance amplifier to the gate of the synchronous rectifier FET; and delivering the output of the comparator to the gate of the synchronous rectifier FET via a switch.
 14. The method of claim 13, further comprising coupling the source of the synchronous rectifier FET to a low reference level.
 15. The method of claim 13, wherein there is a parasitic diode of the synchronous rectifier FET, and the drain signal of the synchronous rectifier FET goes negative when the parasitic diode is on.
 16. The method of claim 15, wherein the synchronous rectifier FET is turned on according to the “on” state of the parasitic diode; and and when the synchronous rectifier FET is turned on, the parasitic diode is off.
 17. The method of claim 13, further comprising turning off the synchronous rectifier FET by the output of the transconductance amplifier if the drain signal of the synchronous rectifier FET increases slowly; and turning off the synchronous rectifier FET by the output of the comparator via the switch if the drain signal of the synchronous rectifier FET increases fast.
 18. A smart driver, comprising: a first means for controlling a synchronous rectifier FET by amplifying the difference between a drain signal of the synchronous rectifier FET and a first DC offset; a second means for controlling the synchronous rectifier FET by comparing the drain signal of the synchronous rectifier FET with a second DC offset; wherein the first means turns on the synchronous rectifier FET when the drain signal is negative, and turns off the synchronous rectifier FET when the drain signal increases slowly and the second means turns off the synchronous rectifier FET when the drain signal increases quickly.
 19. The smart driver as set forth in claim 18, wherein the second means turns off the synchronous rectifier FET via a switch.
 20. The smart driver as set forth in claim 18, wherein there exists a voltage difference between the first DC offset and the second DC offset.
 21. The smart driver as set forth in claim 18, wherein there is a parasitic diode coming with the synchronous rectifier FET, when the parasitic diode is on, the drain signal is negative; when the synchronous rectifier FET is turned on, the parasitic diode is off.
 22. A method comprising: turning on a synchronous rectifier FET when drain signal of the synchronous rectifier FET is negative; and turning off the synchronous rectifier FET when the drain signal goes up.
 23. The method of claim 22, wherein turning off the synchronous rectifier FET by a transconductance amplifier when the drain signal increases slowly; and turning off the synchronous rectifier FET by a comparator when the drain signal increases quickly.
 24. The method of claim 23, wherein the comparator turns off the synchronous rectifier FET via a switch.
 25. The method as set forth in claim 23, further comprising comparing the drain signal with a first DC offset by the transconductance amplifier; and comparing the drain signal with a second DC offset by the comparator; wherein there exists a voltage difference between the first DC offset and the second DC offset.
 26. The method as set forth in claim 22, wherein there is a parasitic diode coming with the synchronous rectifier FET, the drain signal is negative when the parasitic diode is on and when the synchronous rectifier FET is turned on the parasitic diode is off. 